1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and particularly relates to a semiconductor device on which a wafer-level burn-in test is performed and manufacturing method thereof.
2. Description of Related Art
On a semiconductor device represented by a DRAM (Dynamic Random Access Memory), an acceleration test referred to as “burn-in test” is generally performed before shipment. In the burn-in test, a stress such as a high voltage is applied on a semiconductor device for exposing initial defects. While a normal burn-in test is performed in a state of a chip cut out of a silicon wafer, in recent years, the burn-in test is also performed in a state of a silicon wafer. Such a burn-in test is referred to as “wafer-level burn-in test” (see Japanese Patent Application Laid-open No. 2001-250398).
Because the wafer-level burn-in test is performed in parallel on a large number of semiconductor devices on a wafer, external terminals to be used are considerably limited. Specifically, a command terminal and a clock terminal used in a normal operation are not used, and only some of address terminals and test terminals are connected to a tester. Accordingly, during the wafer-level burn-in test, an external clock signal is not supplied to each of the semiconductor devices either.
However, when an external clock signal is not supplied to a semiconductor device, an operation of a circuit that generates an internal clock signal (for example, a DLL circuit) is also stopped, and thus the logic level of a clock tree line that transmits the internal clock signal is fixed. Because the clock tree line is configured by cascade-connecting a large number of CMOS inverter circuits to each other, when the logic level is fixed, a phenomenon referred to as “NBTI (Negative Bias Temperature Instability) degradation” occurs in a P-channel MOS transistor that constitutes a CMOS inverter circuit. The NBTI degradation is a phenomenon in which a threshold voltage is increased when the P-channel MOS transistor is kept to be turned on for a long time. Accordingly, when the NBTI degradation occurs in the clock tree line, the duty of the internal clock signal is changed. The present inventor has found out that the NBTI degradation occurs also during a wafer-level burn-in test.